1. Technical Field
The present invention relates in general to designing, simulating and configuring digital devices, modules and systems, and in particular, to methods and systems for computer-aided design, simulation, and configuration of digital devices, modules and systems described by a hardware description language (HDL) model.
2. Description of the Related Art
In a conventional automated design process utilizing an electronic computer-aided design (ECAD) system, a designer enters a high-level description of a digital design utilizing a hardware description language (HDL), such as VHDL, producing a digital representation of various circuit blocks and their interconnections. The ECAD system compiles the design description into a format (often called a simulation model) that is best suited for simulation. A simulator is then utilized to verify the logical correctness of the digital design prior to developing a circuit layout.
A simulator is typically a software tool that applies a list of input stimuli representing inputs of the digital design to the simulation model to generate a numerical representation of the response of the digital design. The numerical representation of the response may then either be presented on a display as a list of values or further interpreted, often by a separate software program, and presented in graphical form.
As discussed in detail in above-referenced U.S. patent application Ser. No. 10/366,438, the accuracy and completeness of the simulation data generated by the simulator can be improved by the designer including, within the HDL files defining the functional portion of the simulation model, references to instrumentation entities. These instrumentation entities, although not forming a functional portion of the digital design, can perform a number of important checking functions during simulation. Such instrumentation entities can include, for example, logical failure detectors and event and cycle counters.
The designer's control of the simulation and operation of a digital design can be further enhanced by the definition of configuration constructs (e.g., Dials) within the HDL files specifying the digital design. As described in detail in above-referenced U.S. patent application Ser. No. 10/425,076, Dials can be logically connected to the various configuration latches distributed throughout a digital design in order to provide a well-defined interface through which appropriate configuration values may be loaded into the configuration latches.
The present invention recognizes that while instrumentation entities have been defined to monitor and collect simulation data regarding the operation of the design entities comprising the functional portion of a digital design under simulation, heretofore there has been no convenient method and system for generating instrumentation entities to collect simulation data regarding configuration constructs, such as Dials. In particular, prior to the present invention, there has been no automated method and system for generating instrumentation entities to collect important simulation data, such as the number of testcases and simulation cycles that have been executed for each combination of configuration latch settings.